View DS1859_151452.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Rev 1; 11/03
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors
General Description
The DS1859 dual, temperature-controlled, nonvolatile (NV) variable resistors with three monitors consists of two 50k or two 20k, 256-position, linear, variable resistors; three analog monitor inputs (MON1, MON2, MON3); and a direct-to-digital temperature sensor. The device provides an ideal method for setting and temperature-compensating bias voltages and currents in control applications using minimal circuitry. The variable resistor settings are stored in EEPROM memory and can be accessed over the 2-wire serial bus.
Features
SFF-8472 Compatible Five Monitored Channels (Temperature, VCC, MON1, MON2, MON3) Three External Analog Inputs (MON1, MON2, MON3) That Support Internal and External Calibration Scalable Dynamic Range for External Analog Inputs Internal Direct-to-Digital Temperature Sensor Alarm and Warning Flags for All Monitored Channels Two 50k or Two 20k, Linear, 256-Position, Nonvolatile Temperature-Controlled Variable Resistors Resistor Settings Changeable Every 2C Access to Monitoring and ID Information Configurable with Separate Device Addresses 2-Wire Serial Interface Two Buffers with TTL/CMOS-Compatible Inputs and Open-Drain Outputs Operates from a 3.3V or 5V Supply Operating Temperature Range of -40C to +95C
DS1859
Applications
Optical Transceivers Optical Transponders Instrumentation and Industrial Controls RF Power Amps Diagnostic Monitoring
Ordering Information
PART DS1859E-050 DS1859E-020 RESISTANCE 50k 20k 50k 20k 50k 20k PIN-PACKAGE 16 TSSOP 16 TSSOP 16 TSSOP (Tape-and-Reel) 16 TSSOP (Tape-and-Reel) 16-Ball CSBGA 16-Ball CSBGA
Typical Operating Circuit
DS1859E-050/T&R DS1859E-020/T&R
VCC VCC = 3.3V 4.7k 2-WIRE INTERFACE Tx-FAULT 4.7k 1 2 3 4 5 LOS GROUND TO DISABLE WRITE PROTECT 6 7 8 SDA SCL OUT1 IN1 OUT2 IN2 WPEN GND VCC H1 L1 16 15 14 DECOUPLING CAP
DS1859B-050 DS1859B-020
0.1F
TO LASER BIAS CONTROL TO LASER MODULATION CONTROL A
Pin Configurations
TOP VIEW IN1 SCL VCC H1 1 SDA 2 SCL B OUT2 SDA H0 3 OUT1 L1 4 IN1 C WPEN IN2 OUT1 5 OUT2 MON3 6 IN2 7 WPEN MON2 4 8 GND VCC 16 H1 15 L1 14 H0 13
DS1859
13 H0 12 L0 MON3 MON2 MON1
11 Rx POWER* 10 Tx POWER* 9 Tx BIAS* DIAGNOSTIC INPUTS
DS1859
L0 12 MON3 11 MON2 10 MON1 9
*SATISFIES SFF-8472 COMPATIBILITY
D
GND 1
L0 2
MON1 3
CSBGA (4mm x 4mm) 1.0mm PITCH
TSSOP
______________________________________________ Maxim Integrated Products
1
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Relative to Ground ...........-0.5V to +6.0V Voltage Range on Inputs Relative to Ground* ................................................-0.5V to VCC + 0.5V Voltage Range on Resistor Inputs Relative to Ground* ................................................-0.5V to VCC + 0.5V Current into Resistors............................................................5mA *Not to exceed 6.0V.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature Range ...........................-40C to +95C Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature .......................................See IPC/JEDEC J-STD-020A
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +95C, unless otherwise noted.)
PARAMETER Supply Voltage Input Logic 1 (SDA, SCL, WPEN) Input Logic 0 (SDA, SCL, WPEN) Resistor Inputs (L0, L1, H0, H1) Resistor Current High-Z Resistor Current Input Logic Levels (IN1, IN2) IRES IROFF Input logic 1 Input logic 0 1.5 0.9 SYMBOL VCC VIH VIL (Note 1) (Note 2) (Note 2) CONDITIONS MIN 2.97 0.7 x Vcc -0.3 -0.3 -3 0.001 TYP MAX 5.5 VCC + 0.3 +0.3 x VCC VCC + 0.3 +3 0.1 UNITS V V V V mA A V
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.97V to 5.5V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER Supply Current Input Leakage Low-Level Output Voltage (SDA, OUT1, OUT2) Full-Scale Input (MON1, MON2, MON3) Full-Scale VCC Monitor I/O Capacitance WPEN Pullup Digital Power-On Reset Analog Power-On Reset CI/O RWPEN POD POA 40 1.0 2.0 65 SYMBOL ICC IIL VOL1 VOL2 3mA sink current 6mA sink current At factory setting (Note 4) At factory setting (Note 5) CONDITIONS (Note 3) -200 0 0 2.4875 6.5208 2.5 6.5536 MIN TYP 1 MAX 2 +200 0.4 0.6 2.5125 6.5864 10 100 2.2 2.6 UNITS mA nA V V V pF k V V
2
_____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors
ANALOG RESISTOR CHARACTERISTICS
(VCC = 2.97V to 5.5V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER Position 00h Resistance (50k) Position FFh Resistance (50k) Position 00h Resistance (20k) Position FFh Resistance (20k) Absolute Linearity Relative Linearity Temperature Coefficient SYMBOL TA = +25C TA = +25C TA = +25C TA = +25C (Note 6) (Note 7) (Note 8) CONDITIONS MIN 0.65 40 0.20 16 -2 -1 50 TYP 1.0 50 0.40 20 MAX 1.35 60 0.55 24 +2 +1 UNITS k k k k LSB LSB ppm/C
DS1859
ANALOG VOLTAGE MONITORING
(VCC = 2.97V to 5.5V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER Input Resolution Supply Resolution Input/Supply Accuracy (MON1, MON2, MON3, VCC) Update Rate for MON1, MON2, MON3, Temp, or VCC Input/Supply Offset (MON1, MON2, MON3, VCC) SYMBOL VMON VCC ACC tframe VOS (Note 14) At factory setting CONDITIONS MIN TYP 610 1.6 0.25 30 0 0.5 45 5 MAX UNITS V mV % FS (full scale) ms LSB
DIGITAL THERMOMETER
(VCC = 2.97V to 5.5V, TA = -40C to +95C, unless otherwise noted.)
PARAMETER Thermometer Error SYMBOL TERR CONDITIONS -40C to +95C MIN TYP MAX 3.0 UNITS C
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = 2.97V to 5.5V)
PARAMETER EEPROM Writes SYMBOL +70C CONDITIONS MIN 50,000 TYP MAX UNITS
_____________________________________________________________________
3
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.97V to 5.5V, TA = -40C to +95C, unless otherwise noted. See Figure 6.)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Condition Hold Time (Repeated) START Condition LOW Period of SCL Clock HIGH Period of SCL Clock Data Hold Time Data Setup Time START Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Setup Time for STOP Condition Capacitive Load for Each Bus Line EEPROM Write Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tR tF tSU:STO CB tW CONDITIONS Fast mode (Note 9) Standard mode (Note 9) Fast mode (Note 9) Standard mode (Note 9) Fast mode (Notes 9, 10) Standard mode (Notes 9, 10) Fast mode (Note 9) Standard mode (Note 9) Fast mode (Note 9) Standard mode (Note 9) Fast mode (Notes 9, 11, 12) Standard mode (Notes 9, 11, 12) Fast mode (Note 9) Standard mode (Note 9) Fast mode (Note 9) Standard mode (Note 9) Fast mode (Note 13) Standard mode (Note 13) Fast mode (Note 13) Standard mode (Note 13) Fast mode Standard mode (Note 13) (Note 14) 10 MIN 0 0 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0 0 100 250 0.6 4.7 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 4.0 400 20 300 1000 300 300 0.9 TYP MAX 400 100 UNITS kHz s s s s s ns s ns ns s pF ms
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
All voltages are referenced to ground. I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off. SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels. Full Scale is user programmable. The maximum voltage that the MON inputs read is approximately Full Scale, even if the voltage on the inputs is greater than Full Scale. This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum VCC voltage. Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a straight line from measured minimum position to measured maximum position. Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change is the slope of the straight line from measured minimum position to measured maximum position. See the Typical Operating Characteristics. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released.
4
_____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors
Note 10: After this period, the first clock pulse is generated. Note 11: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIH MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 13: CB--total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC. Note 14: Guaranteed by design.
DS1859
Typical Operating Characteristics
(VCC = 5.0V, TA = +25C, for both 50k and 20k versions, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
DS1859 toc01
SUPPLY CURRENT vs. VOLTAGE
DS1859 toc02
RESISTANCE vs. SETTING
50k VERSION 50 RESISTANCE (k) 40 30 20 10 0
DS1859 toc03
720 SDA = SCL = VCC 680 SUPPLY CURRENT (A)
700 SDA = SCL = VCC 650 SUPPLY CURRENT (A) 600 550 500 450 400
60
640
600
560
520 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
3.0
3.5
4.0
4.5
5.0
5.5
0
50
100
150
200
250
VOLTAGE (V)
SETTING (DEC)
RESISTANCE vs. SETTING
20k VERSION 15 RESISTANCE (k)
DS1859 toc04
ACTIVE SUPPLY CURRENT vs. SCL FREQUENCY
DS1859 toc05
RESISTOR 0 INL (LSB)
0.8 0.6 RESISTOR 0 INL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
DS1859 toc06
20
760 SDA = VCC ACTIVE SUPPLY CURRENT (A) 720
1.0
680
10
640
5
600
0 0 50 100 150 200 250 SETTING (DEC)
560 0 100 200 300 400 SCL FREQUENCY (kHz)
-1.0 0 25 50 75 100 125 150 175 200 225 250 SETTING (DEC)
_____________________________________________________________________
5
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Typical Operating Characteristics (continued)
(VCC = 5.0V, TA = +25C, for both 50k and 20k versions, unless otherwise noted.)
RESISTOR 0 DNL (LSB)
DS1859 toc07
RESISTOR 1 INL (LSB)
DS1859 toc08
RESISTOR 1 DNL (LSB)
0.8 0.6 RESISTOR 1 DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
DS1859 toc09
1.0 0.8 0.6 RESISTOR 0 DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0
1.0 0.8 0.6 RESISTOR 1 INL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
1.0
25 50 75 100 125 150 175 200 225 250 SETTING (DEC)
0
25 50 75 100 125 150 175 200 225 250 SETTING (DEC)
0
25 50 75 100 125 150 175 200 225 250 SETTING (DEC)
RESISTANCE vs. POWER-UP VOLTAGE
DS1859 toc10
RESISTANCE vs. POWER-UP VOLTAGE
110 100 RESISTANCE (k) 90 80 70 60 50 40 30 20 10 0 PROGRAMMED RESISTANCE (80h) >1M 20k VERSION
DS1859 toc11
120 110 100 RESISTANCE (k) 90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 POWER-UP VOLTAGE (V) PROGRAMMED RESISTANCE (80h) >1M 50k VERSION
120
0
1
2
3
4
5
POWER-UP VOLTAGE (V)
POSITION 00h RESISTANCE vs. TEMPERATURE
50k VERSION 0.99 RESISTANCE (k)
DS1859 toc12
1.00
0.98
0.97
0.96
0.95 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C)
6
_____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Typical Operating Characteristics (continued)
(VCC = 5.0V, TA = +25C, for both 50k and 20k versions, unless otherwise noted.)
POSITION 00h RESISTANCE vs. TEMPERATURE
DS1859 toc13
POSITION FFh RESISTANCE vs. TEMPERATURE
DS1859 toc14
POSITION FFh RESISTANCE vs. TEMPERATURE
20k VERSION 19.80 RESISTANCE (k)
DS1859 toc15
0.38 20k VERSION 0.37 RESISTANCE (k)
52.00 50k VERSION 51.80 RESISTANCE (k)
20.00
0.36
51.60
19.50
0.35
51.40
19.40
0.34
51.20
19.20
0.33 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C)
51.00 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C)
19.00 -40 -25 -10 5 20 35 50 65 80 95 TEMPERATURE (C)
TEMPERATURE COEFFICIENT vs. SETTING
DS1859 toc16
TEMPERATURE COEFFICIENT vs. SETTING
TEMPERATURE COEFFICIENT (ppm/C) 700 600 500 400 300 200 100 0 -100 0 50 100 150 200 250 +25C TO +95C +25C TO -40C 20k VERSION
DS1859 toc17
400 TEMPERATURE COEFFICIENT (ppm/C) 350 300 250 200 150 100 50 0 -50 -100 0 50 100 150 200 +25C TO +95C +25C TO -40C 50k VERSION
800
250
SETTING (DEC)
SETTING (DEC)
LSB ERROR vs. FULL-SCALE INPUT
6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 0 25
DS1859 toc18
LSB ERROR vs. FULL-SCALE INPUT
+3 SIGMA 2 1
DS1859 toc19
3
+3 SIGMA
LSB ERROR
MEAN
LSB ERROR
0 -1 -2
MEAN
-3 SIGMA
-3 -4
-3 SIGMA 0 3.125 6.250 9.375 12.500
50
75
100
NORMALIZED FULL SCALE (%)
NORMALIZED FULL SCALE (%)
_______________________________________________________________________________________
7
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 BALL B2 A2 C3 A1 B1 C2 C1 D1 D3 D4 C4 D2 NAME SDA SCL OUT1 IN1 OUT2 IN2 WPEN GND MON1 MON2 MON3 L0 FUNCTION 2-Wire Serial Data I/O Pin. Transfers serial data to and from the device. 2-Wire Serial Clock Input. Clocks data into and out of the device. Open-Drain Buffer Output TTL/CMOS-Compatible Input to Buffer Open-Drain Buffer Output TTL/CMOS-Compatible Input to Buffer Write Protect Enable. The device is not write protected if WPEN is connected to ground. This pin has an internal pullup (RWPEN). See Table 6. Ground External Analog Input External Analog Input External Analog Input Low-End Resistor 0 Terminal. It is not required that the low-end terminals be connected to a potential less than the high-end terminals of the corresponding resistor. Voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground. High-End Resistor 0 Terminal. It is not required that the high-end terminals be connected to a potential greater than the low-end terminals of the corresponding resistor. Voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground. Low-End Resistor 1 Terminal High-End Resistor 1 Terminal Supply Voltage
13 14 15 16
B3 B4 A4 A3
H0 L1 H1 VCC
Detailed Description
The user can read the registers that monitor the VCC, MON1, MON2, MON3, and temperature analog signals. After each signal conversion, a corresponding bit is set that can be monitored to verify that a conversion has occurred. The signals also have alarm and warning flags that notify the user when the signals go above or below the user-defined value. Interrupts can also be set for each signal. The position values of each resistor can be independently programmed. The user can assign a unique value to each resistor for every 2C increment over the -40C to +102C range.
Two buffers are provided to convert logic-level inputs into open-drain outputs. Typically, these buffers are used to implement transmit (Tx) fault and loss-of-signal (LOS) functionality. Additionally, OUT1 can be asserted in the event that one or more of the monitored values go beyond user-defined limits.
8
_____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
PROT AUX AD (AUXILIARY DEVICE ENABLE A0h) TABLE SELECT MD (MAIN DEVICE ENABLE) DEVICE ADDRESS ADDRESS R/W ADEN ADFIX SDA 2-WIRE INTERFACE SCL R/W Tx FAULT OUT1 ADDRESS MINT EEPROM 96 x 8 BIT 00h-5Fh LIMITS REGISTER MONITORS LIMIT HIGH MONITORS LIMIT LOW TxF PROT MAIN MD H0 RESISTOR 0 50k OR 20k FULL SCALE 256 POSITIONS L0 EEPROM 128 x 8 BIT 00h-7Fh STANDARDS EEPROM 72 x 8 BIT 80h-C7h TABLE 02 RESISTOR 0 LOOK-UP TABLE TABLE SELECT EEPROM 72 x 8 BIT 80h-C7h TABLE 03 RESISTOR 1 LOOK-UP TABLE AD PROT MAIN MD PROT MAIN MD
DEVICE ADDRESS
ADDRESS R/W
ADDRESS R/W
ADDRESS DATA BUS TEMP INDEX TEMP INDEX
R/W
TEMP INDEX INV1 RxL OUT2 LOS TxF MINT (BIT) REGISTER IN1 SRAM 32 x 8 BIT 60h-7Fh NOT PROTECTED
H1 RESISTOR 1 50k OR 20k FULL SCALE 256 POSITIONS L1 PROT MAIN
TABLE SELECT MEASUREMENT INV2 RIGHT SHIFTING
WARNING FLAGS
MD
R/W INV1 (BIT)
ALARM FLAGS
IN2 TABLE SELECT VCC INTERNAL TEMP INTERNAL CALIBRATION ADDRESS TABLE 01 EEPROM 16 x 8 BIT 80h-8Fh VENDOR
INV2 (BIT) APEN (BIT) MPEN (BIT) ADEN (BIT) ADFIX (BIT)
DS1859
MON1 MON2 MON3 VCC RWPEN MUX CTRL APEN PROT AUX COMPARATOR COMP CTRL PROT MAIN WARNING FLAGS ALARM FLAGS A/D CTRL VCC VCC GND MPEN MONITORS LIMIT HIGH MONITORS LIMIT LOW MEASUREMENT MUX ADC 12-BIT DEVICE ADDRESS
MASKING (TMP, VCC, MON1, MON2, MON3) MINT INTERRUPT
WPEN
Figure 1. Block Diagram
_____________________________________________________________________
9
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Table 1. Scales for Monitor Channels at Factory Setting
SIGNAL Temperature VCC MON1 MON2 MON3 +FS SIGNAL 127.984C 6.5528V 2.4997V 2.4997V 2.4997V +FS (hex) 7FFC FFF8 FFF8 FFF8 FFF8 -FS SIGNAL -128C 0V 0V 0V 0V -FS (hex) 8000 0000 0000 0000 0000
Table 3. Look-up Table Address for Corresponding Temperature Values
TEMPERATURE (C) <-40 -40 -38 -36 -34 -- +98 CORRESPONDING LOOK-UP TABLE ADDRESS 80h 80h 81h 82h 83h -- C5h C6h C7h C7h
Table 2. Signal Comparison
SIGNAL VCC MON1 MON2 MON3 Temperature FORMAT Unsigned Unsigned Unsigned Unsigned Two's complement
+100 +102 >+102
Monitor Conversion Example
MSB (BIN) 11000000 10000000 LSB (BIN) 00000000 10000000 VOLTAGE (V) 1.875 1.255
Monitored Signals
Each signal (VCC, MON1, MON2, MON3, and temperature) is available as a 16-bit value with 12-bit accuracy (left-justified) over the serial bus. See Table 1 for signal scales and Table 2 for signal format. The four LSBs should be masked when calculating the value. For the 20k version, the 3 LSBs are internally masked with 0s. The signals are updated every frame rate (tframe) in a round-robin fashion. The comparison of all five signals with the high and low user-defined values are done automatically. The corresponding flags are set to 1 within a specified time of the occurrence of an out-of-limit condition. Calculating Signal Values The LSB = 100V for VCC, and the LSB = 38.147V for the MON signals when using factory default settings.
To calculate VCC, convert the unsigned 16-bit value to decimal and multiply by 100V. To calculate MON1, MON2, or MON3, convert the unsigned 16-bit value to decimal and multiply by 38.147V. To calculate the temperature, treat the two's complement value binary number as an unsigned binary number, then convert to decimal and divide by 256. If the result is greater than or equal to 128, subtract 256 from the result. Temperature: high byte: -128C to +127C signed; low byte: 1/256C.
Temperature Bit Weights
S 2-1 26 2-2 25 2-3 24 2-4 23 2-5 22 2-6 21 2-7 20 2-8
Monitor/VCC Bit Weights
MSB LSB 215 27 214 26 213 25 212 24 211 23 210 22 29 21 28 20
Temperature Conversion Examples
MSB (BIN) 01000000 01000000 LSB (BIN) 00000000 00001111 00000000 00000000 00000000 TEMPERATURE (C) 64 64.059 95 -10 -40
VCC Conversion Examples
MSB (BIN) 10000000 11000000 LSB (BIN) 10000000 11111000 VOLTAGE (V) 3.29 4.94
01011111 11110110 11011000
10
____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Table 4. ADEN Address Configuration
ADEN (ADDRESS ENABLE) 0 1 NO. OF SEPARATE DEVICE ADDRESSES 2 1 (Main Device only) ADDITIONAL INFORMATION See Figure 2 See Figure 3
Table 5. ADEN and ADFIX Bits
ADEN 0 0 1 1 ADFIX 0 1 0 1 AUXILIARY ADDRESS A0h A0h N/A N/A MAIN ADDRESS A2h EEPROM (Table 01, 8Ch) A2h EEPROM (Table 01, 8Ch)
MAIN DEVICE ENABLE AUXILIARY DEVICE ENABLE DEC 0 AUXILIARY DEVICE EN 60h 95 96 127 128 143 F0h 199 RESERVED FFh F0h RESERVED FFh EN 7Fh 7Fh TABLE SELECT DECODER TABLE 01 TABLE 02 TABLE 03 EN EN EN 80h 80h 80h MON LOOK-UP TABLE CONTROL R1 LOOK-UP R0 LOOK-UP TABLE TABLE SEL 8Fh SEL C7h SEL C7h MAIN DEVICE EN 0 0
5Fh
MEMORY PARTITION WITH ADEN BIT = 0
Figure 2. Memory Organization, ADEN = 0
Variable Resistors
The value of each variable resistor is determined by a temperature-addressed look-up table, which can assign a unique value (00h to FFh) to each resistor for every 2C increment over the -40C to +102C range (see Table 3). See the Temperature Conversion section for more information. The variable resistors can also be used in manual mode. If the TEN bit equals 0, the resistors are in manual mode and the temperature indexing is disabled. The user sets the resistors in manual mode by writing to addresses 82h and 83h in Table 01 to control resistors 0 and 1, respectively.
Memory Description
Main and auxiliary memories can be accessed by two separate device addresses. The Main Device address is A2h (or value in Table 01 byte 8Ch, when ADFIX = 1) and the Auxiliary Device address is A0h. A user option is provided to respond to one or two device addresses. This feature can be used to save component count in SFF applications (Main Device address can be used) or other applications where both GBIC (Auxiliary Device address can be used) and monitoring functions are implemented and two device addresses are needed. The memory blocks are enabled with the corresponding device address. Memory space from 80h and
11
____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
MAIN DEVICE ENABLE 0 DEC 0 MAIN DEVICE 60h 95 96 127 128 143 EN 7Fh TABLE 00 80h TABLE SELECT DECODER TABLE 01 TABLE 02 TABLE 03 EN EN EN 80h 80h 80h MON LOOK-UP TABLE CONTROL R1 LOOK-UP R0 LOOK-UP TABLE TABLE SEL 8Fh SEL C7h F0h RESERVED FFh 255 FFh MEMORY PARTITION WITH ADEN BIT = 1 F0h RESERVED FFh SEL C7h EN
5Fh
AUXILIARY DEVICE EN
199
Figure 3. Memory Organization, ADEN = 1
above is accessible only through the Main Device address. This memory is organized as three tables. The desired table can be selected by the contents of memory location 7Fh, Main Device. The Auxiliary Device address has no access to the tables, but the Auxiliary Device address can be mapped into the Main Device's memory space as a fourth table. Device addresses are programmable with two control bits in EEPROM.
Table 6. Main Device
WPEN 0 X 1 MPEN X 0 1 PROTECT MAIN No No Yes
ADEN configures memory access to respond to different device addresses (see Tables 4 and 5). The default device address for EEPROM-generated addresses is A2h. If the ADEN bit is 1, additional 128 bytes of EEPROM are accessible through the Main Device, selected as Table 00 (see Figure 3). In this configuration, the Auxiliary Device is not accessible. APEN controls the protection of Table 00 regardless of ADEN's setting. ADFIX (address fixed) determines whether the Main Device address is determined by an EEPROM byte (Table 01, byte 8Ch, when ADFIX = 1). There can be up to 128 devices sharing a common 2-wire bus, with each device having its own unique device address.
Table 7. Auxiliary Device
APEN 0 1 WPEN X X PROTECT AUXILIARY No Yes
12
____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors
Register Map
A description of the registers is below. The registers are read only (R) or read/write (R/W). The R/W registers are writable only if write protect has not been asserted (see the Memory Description section). Bytes designated as "Reserved" have been set aside for added functionality in future revisions of this device.
DS1859
Auxiliary Device
MEMORY LOCATION (hex) 00 to 7F EEPROM/SRAM EEPROM R/W R/W DEFAULT SETTING (hex) 00 NAME OF LOCATION Standards Data FUNCTION --
Main Device
MEMORY LOCATION (hex) EEPROM/ SRAM R/W DEFAULT SETTING (hex) NAME OF LOCATION FUNCTION
00 to 01
EEPROM
R/W
00
TMPlimhi (MSB to LSB)
Contains upper limit settings for temperature. If the limit is violated, an alarm flag in Main Device byte 70h is set. Contains lower limit settings for temperature. If the limit is violated, an alarm flag in Main Device byte 70h is set. Contains upper limit settings for temperature. If the limit is violated, a warning flag in Main Device byte 74h is set. Contains lower limit settings for temperature. If the limit is violated, a warning flag in Main Device byte 74h is set. Contains upper limit settings for VCC. If the limit is violated, an alarm flag in Main Device byte 70h is set. Contains lower limit settings for VCC. If the limit is violated, an alarm flag in Main Device byte 70h is set. Contains upper limit settings for VCC. If the limit is violated, a warning flag in Main Device byte 74h is set. Contains lower limit settings for VCC. If the limit is violated, a warning flag in Main Device byte 74h is set. Contains upper limit settings for MON1. If the limit is violated, an alarm flag in Main Device byte 70h is set.
02 to 03
EEPROM
R/W
00
TMPlimlo (MSB to LSB)
04 to 05
EEPROM
R/W
00
TMPwrnhi (MSB to LSB)
06 to 07
EEPROM
R/W
00
TMPwrnlo (MSB to LSB)
08 to 09
EEPROM
R/W
00
VCClimhi (MSB to LSB)
0A to 0B
EEPROM
R/W
00
VCClimlo (MSB to LSB)
0C to 0D
EEPROM
R/W
00
VCCwrnhi (MSB to LSB)
0E to 0F
EEPROM
R/W
00
VCCwrnlo (MSB to LSB)
10 to 11
EEPROM
R/W
00
MON1limhi (MSB to LSB)
Note: SRAM defaults are power-on defaults. EEPROM defaults are factory defaults. ____________________________________________________________________ 13
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Main Device (continued)
MEMORY LOCATION (hex) EEPROM/ SRAM R/W DEFAULT SETTING (hex) NAME OF LOCATION FUNCTION
12 to 13
EEPROM
R/W
00
MON1limlo (MSB to LSB)
Contains lower limit settings for MON1. If the limit is violated, an alarm flag in Main Device byte 70h is set. Contains upper limit settings for MON1. If the limit is violated, a warning flag in Main Device byte 74h is set. Contains lower limit settings for MON1. If the limit is violated, a warning flag in Main Device byte 74h is set. Contains upper limit settings for MON2. If the limit is violated, an alarm flag in Main Device byte 70h is set. Contains lower limit settings for MON2. If the limit is violated, an alarm flag in Main Device byte 70h is set. Contains upper limit settings for MON2. If the limit is violated, a warning flag in Main Device byte 74h is set. Contains lower limit settings for MON2. If the limit is violated, a warning flag in Main Device byte 74h is set. Contains upper limit settings for MON3. If the limit is violated, an alarm flag in Main Device byte 71h is set. Contains lower limit settings for MON3. If the limit is violated, an alarm flag in Main Device byte 71h is set. Contains upper limit settings for MON3. If the limit is violated, a warning flag in Main Device byte 75h is set. Contains lower limit settings for MON3. If the limit is violated, a warning flag in Main Device byte 75h is set. -- -- Digitized measured value for temperature. See Table 1. Digitized measured value for VCC. See Table 1. Digitized measured value for MON1. See Table 1. Digitized measured value for MON2. See Table 1.
14 to 15
EEPROM
R/W
00
MON1wrnhi (MSB to LSB)
16 to 17
EEPROM
R/W
00
MON1wrnlo (MSB to LSB)
18 to 19
EEPROM
R/W
00
MON2limhi (MSB to LSB)
1A to 1B
EEPROM
R/W
00
MON2limlo (MSB to LSB) MON2wrnhi (MSB to LSB) MON2wrnlo (MSB to LSB)
1C to 1D
EEPROM
R/W
00
1E to 1F
EEPROM
R/W
00
20 to 21
EEPROM
R/W
00
MON3limhi (MSB to LSB)
22 to 23
EEPROM
R/W
00
MON3limlo (MSB to LSB)
24 to 25
EEPROM
R/W
00
MON3wrnhi (MSB to LSB) MON3wrnlo (MSB to LSB) Reserved Memory Measured TMP (MSB to LSB) Measured VCC (MSB to LSB) Measured MON1 (MSB to LSB) Measured MON2 (MSB to LSB)
26 to 27 28 to 37 38 to 5F 60 to 61 62 to 63 64 to 65 66 to 67
EEPROM EEPROM EEPROM SRAM SRAM SRAM SRAM
R/W -- R/W R R R R
00 -- -- -- -- -- --
14
____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Main Device (continued)
MEMORY LOCATION (hex) 68 to 69 6A to 6D 6E EEPROM/ SRAM SRAM SRAM SRAM R/W DEFAULT SETTING (hex) -- -- -- NAME OF LOCATION Measured MON3 (MSB to LSB) Reserved Logic states FUNCTION Digitized measured value for MON3. See Table 1. -- -- Resistor status bit. A high indicates that both resistors are in high-impedance mode. A low indicates that both resistors are operating normally. Resistor control bit. Setting this bit high causes both resistors to go into a highimpedance state. -- -- This status bit is high when OUT1 is high, assuming there is an external pullup resistor on OUT1. -- This status bit is high when OUT2 is high, assuming there is an external pullup resistor on OUT2. This status bit goes high when VCC has fallen below the POA level. -- This bit goes high after a temperature and address update has occurred for the corresponding measurement in bytes 60h to 61h. This bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. This bit goes high after a VCC update has occurred for the corresponding measurement in bytes 62h to 63h. This bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. This bit goes high after a MON1 update has occurred for the corresponding measurement in bytes 64h to 65h. This bit can be written to a 0 by the user and monitored to verify that a conversion has occurred.
R -- --
Bit 7
--
R
X
HIZSTA
6 5 4 2 3 1
-- -- -- -- -- --
R/W -- -- R -- R
0 X X X X X
HIZCO X X TXF X RXL
0 6F
-- SRAM
R --
X --
RDYB Conversion updates
Bit 7
--
R/W
0
TAU
6
--
R/W
0
VCCU
5
--
R/W
0
MON1U
____________________________________________________________________
15
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Main Device (continued)
MEMORY LOCATION (hex) EEPROM/ SRAM R/W DEFAULT SETTING (hex) NAME OF LOCATION FUNCTION This bit goes high after a MON2 update has occurred for the corresponding measurement in bytes 66h to 67h. This bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. This bit goes high after a MON3 update has occurred for the corresponding measurement in bytes 68h to 69h. This bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. -- -- -- -- This alarm flag goes high when the upper limit of the temperature setting is violated. This alarm flag goes high when the lower limit of the temperature setting is violated. This alarm flag goes high when the upper limit of the VCC setting is violated. This alarm flag goes high when the lower limit of the VCC setting is violated. This alarm flag goes high when the upper limit of the MON1 setting is violated. This alarm flag goes high when the lower limit of the MON1 setting is violated. This alarm flag goes high when the upper limit of the MON2 setting is violated. This alarm flag goes high when the lower limit of the MON2 setting is violated. -- This alarm flag goes high when the upper limit of the MON3 setting is violated. This alarm flag goes high when the lower limit of the MON3 setting is violated. -- --
4
--
R/W
0
MON2U
3
--
--
0
MON3U
2 1 0 70 Bit 7 6 5 4 3 2 1 0 71 Bit 7 6 5 4
-- -- -- SRAM -- -- -- -- -- -- -- -- SRAM -- -- -- --
-- -- -- R -- -- -- -- -- -- -- -- R -- -- -- --
0 0 0
-- -- -- Alarm flags
-- -- -- -- -- -- -- -- -- -- -- -- --
TMPhi TMPlo VCChi VCClo MON1hi MON1lo MON2hi MON2lo Alarm flags MON3hi MON3lo X X
16
____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Main Device (continued)
MEMORY LOCATION (hex) 3 2 1 EEPROM/ SRAM -- -- -- R/W -- -- -- DEFAULT SETTING (hex) -- -- -- NAME OF LOCATION X X X FUNCTION -- -- -- A mask of all flags located in Table 01 byte 88h determines the value of MINT. MINT is maskable to 0 if no interrupt is desired by setting Table 01 byte 88h to 0. -- -- This warning flag goes high when the upper limit of the temperature setting is violated. This warning flag goes high when the lower limit of the temperature setting is violated. This warning flag goes high when the upper limit of the VCC setting is violated. This warning flag goes high when the lower limit of the VCC setting is violated. This warning flag goes high when the upper limit of the MON1 setting is violated. This warning flag goes high when the lower limit of the MON1 setting is violated. This warning flag goes high when the upper limit of the MON2 setting is violated. This warning flag goes high when the lower limit of the MON2 setting is violated.
0
--
--
--
MINT
72 to 73 74 Bit 7 6 5 4 3 2 1 0
SRAM SRAM -- -- -- -- -- -- -- --
-- R -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
Reserved Warning flags TMPhi TMPlo VCChi VCClo MON1hi MON1lo MON2hi MON2lo
____________________________________________________________________
17
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Main Device (continued)
MEMORY LOCATION (hex) 75 Bit 7 6 5 4 3 2 1 76 to 7E 7F Bit 7 6 5 4 3 2 1 0 EEPROM/ SRAM SRAM -- -- -- -- -- -- -- SRAM SRAM -- -- -- -- -- -- -- -- R/W R -- -- -- -- -- -- -- -- R/W -- -- -- -- -- -- -- -- DEFAULT SETTING (hex) -- 0 0 0 0 0 0 0 -- -- 0 0 0 0 0 0 0 Table select bits 0 NAME OF LOCATION Warning Flags MON3hi MON3lo X X X X X Reserved Table select X X X X X X FUNCTION -- This warning flag goes high when the upper limit of the MON3 setting is violated. This warning flag goes high when the lower limit of the MON3 setting is violated. -- -- -- -- -- -- -- -- -- -- -- -- -- Set bits = 00 to select Table 00, set bits = 01 to select Table 01, set bits = 10 to select Table 02, set bits = 11 to select Table 03.
18
____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Table 01h
MEMORY EEPROM/ LOCATION SRAM (hex) 80 Bit 7 6 5 4 3 2 SRAM -- -- -- -- -- -- R/W R/W -- -- -- -- -- -- 0 0 0 0 0 0 DEFAULT SETTING (hex) NAME OF LOCATION Mode X X X X X X FUNCTION -- -- -- -- -- -- -- If TEN = 0, the resistors can be controlled manually. The user sets the resistor in manual mode by writing to addresses 82h and 83h in Table 01 to control resistors 0 and 1, respectively. AEN = 0 is a test mode setting and provides manual control of the temperature index (Table 01, address 81h). This byte is the temperature-calculated index used to select the address of resistor settings in the look-up tables (Tables 02 and 03, addresses 80h through C7h). Resistor 0 position values from 00h to FFh. Resistor 1 position values from 00h to FFh. -- This byte configures a maskable interrupt, determining which event asserts a buffer 1 output (MINT set to 1, see register 89h in Table 01). If any combination of temperature, VCC, MON1, MON2, or MON3 is desired to generate an interrupt, the corresponding bits are set to 1. If interrupt generation is not desired, set all bits to 0. -- -- -- -- -- -- -- -- -- --
1
--
--
1
TEN
0
--
--
1
AEN Temperature index Resistor 0 Resistor 1 Reserved
81 82 83 84 to 87
SRAM SRAM SRAM SRAM
R R/W R/W --
-- FF FF --
88
EEPROM
R/W
Interrupt enable
Bit 7 6 5 4 3 2 1 0 89 Bit 7 6
-- -- -- -- -- -- -- -- EEPROM -- --
-- -- -- -- -- -- -- -- R/W -- --
1 1 1 1 1 0 0 0 0 0
TMP VCC MON1 MON2 MON3 X X X Configuration X X
____________________________________________________________________
19
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Table 01h (continued)
MEMORY EEPROM/ LOCATION SRAM (hex) R/W DEFAULT SETTING (hex) NAME OF LOCATION FUNCTION
5
--
--
0
ADEN
Controls if the device responds to one or two device addresses (see the Memory Description section and Table 5). Controls the means by which Main and Auxiliary Device addresses are set (see the Memory Description section and Table 5). Controls auxiliary write protect. See the Memory Description section. Controls main write protect. See the Memory Description section. Configures buffer 1 with OUT1 = MINT + (INV1 [XOR] IN1). Configures buffer 2 with OUT2 = INV2 [XOR] IN2. Contains Main Device address if the bit ADFIX = 1. If ADFIX = 0, then address A2h is used. -- Contains bits used to perform right shift operations on the A/D output converter. See the Right Shift A/D Conversion Result section.
4
--
--
0
ADFIX
3 2 1 0 8A to 8B 8C 8D 8E 7 6 5 4 3 2 1 0 8F 7 6 5 4 3 2 1 0
-- -- -- -- EEPROM EEPROM EEPROM EEPROM -- -- -- -- -- -- -- -- EEPROM -- -- -- -- -- -- -- --
-- -- -- -- -- R/W -- R/W -- -- -- -- -- -- -- -- R/W -- -- -- -- -- -- -- --
0 0 0 0 -- A2 --
APEN MPEN INV1 INV2 Reserved Device address Reserved
0 0 0 0 0 0 0 0
-- MON12 MON11 MON10 -- MON22 MON21 MON20 Right Shift Control LSB Contains bits used to perform right shift operations on the A/D output converter. See the Right Shift A/D Conversion Result section. Right Shift Control MSB Right Shift Control LSB Right Shift Control MSB
0 0 0 0 0 0 0 0
-- MON32 MON31 MON30 -- -- -- -- Right Shift Control LSB Right Shift Control MSB
20
____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Table 01h (continued)
MEMORY EEPROM/ LOCATION SRAM (hex) 90 to 91 92 to 93 94 to 95 96 to 97 98 to 99 9A to 9F A0 to A1 A2 to A3 A4 to A5 A6 to A7 A8 to A9 AA to AD AE to AF EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM R/W -- R/W R/W R/W R/W -- -- R/W R/W R/W R/W -- R/W Factory Programmed DEFAULT SETTING (hex) 0 NAME OF LOCATION Reserved Gain Cal VCC Gain Cal Mon1 Gain Cal Mon2 Gain Cal Mon3 Reserved Reserved Offset Cal VCC Offset Cal Mon1 Offset Cal Mon2 Offset Cal Mon3 Reserved Offset Cal Tmp Offset calibration for temperature calibrated at factory. Offset registers for internal calibration. See the Internal Calibration section. Gain registers for internal calibration. See the Internal Calibration section. FUNCTION
Table 02h
MEMORY LOCATION (hex) 80 to C7 F0 to F7 F8 to FF EEPROM/ SRAM EEPROM EEPROM EEPROM R/W R/W -- R DEFAULT SETTING (hex) FF -- Factory Programmed NAME OF LOCATION Resistor 0 Temp LUT Reserved Resistor 0 Cal Constants FUNCTION Look-up table for Resistor 0. -- Calibration constants for Resistor 0. (See Table 8)
Table 03h
MEMORY LOCATION (hex) 80 to C7 F0 to F7 F8 to FF EEPROM/ SRAM EEPROM EEPROM EEPROM R/W R/W -- R DEFAULT SETTING (hex) FF -- Factory Programmed NAME OF LOCATION Resistor 1 Temp LUT Reserved Resistor 1 Cal Constants FUNCTION Look-up table for Resistor 1. -- Calibration constants for Resistor 1. (See Table 8)
____________________________________________________________________
21
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Programming the Look-up Table (LUT)
The following equation can be used to determine which resistor position setting, 00h to FFh, should be written in the LUT to achieve a given resistance at a specific temperature.
2 R - u * 1 + v * (C - 25) + w * (C - 25) - pos(, R, C) = 2 (x) * 1 + y * (C - 25) + z * (C - 25) = 3.852357 for the 20k resistor = 4.5680475 for the 50k resistor R = the resistance desired at the output terminal C = temperature in degrees Celsius u, v, w, x1, x0, y, and z are calculated values found in the corresponding look-up tables. The variable x from the equation above is separated into x1 (the MSB of x) and x0 (the LSB of x). Their addresses and LSB values are given below. Resistor 0 variables are found in Table 1, and Resistor 1 variables are found in Table 2.
MEMORY LOCATION M6
M5
DECREASING TEMPERATURE
M4
M3
M2
INCREASING TEMPERATURE
M1
2
4
6 8 TEMPERATURE (C)
10
12
Figure 4. Look-Up Table Hysteresis
When shipped from the factory, all other memory locations in the LUTs are programmed to FFh.
Table 8. Calibration Constants
ADDRESS (Hex) F8 F9 FA FB FC FD FE FF VARIABLE u v w x1 x0 y z Reserved LSB 20 20E-6 100-9 21 2-7 2E-6 10E-9 --
assume that the LSB of the lowest weighted bit is 50V, then the FS value is 65,535 x 50V = 3.27675V). A binary search is used to scale the gain of the converter. This requires forcing two known voltages to the input pin. It is preferred that one of the forced voltages is the null input and the other is 90% of FS. Since the LSB of the least significant bit in the digital reading register is known, the expected digital results are also known for both inputs (null/LSB = CNT1 and 90%FS/ LSB = CNT2). The user might not directly force a voltage on the input. Instead they have a circuit that transforms light, frequency, power, or current to a voltage that is the input to the DS1859. In this situation, the user does not need to know the relationship of voltage to expected digital result but instead knows the relationship of light, frequency, power, or current to the expected digital result.
Internal Calibration
The DS1859 has two methods for scaling an analog input to a digital result. The two methods are gain and offset. Each of the inputs (VCC, MON1, MON2, and MON3) has a unique register for the gain and the offset found in Table 01h, 92h to 99h, and A2h to A9h. To scale the gain and offset of the converter for a specific input, you must first know the relationship between the analog input and the expected digital result. The input that would produce a digital result of all zeros is the null value (normally this input is GND). The input that would produce a digital result of all ones is the fullscale (FS) value. The FS value is also found by multiplying an all-ones digital answer by the weighted LSB (e.g., since the digital reading is a 16-bit register, let us
22
____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors
An explanation of the binary search used to scale the gain is best served with the following example pseudocode: /* Assume that the Null input is 0.5V. */ /* In addition, the requirement for LSB is 50V. */ FS = 65535 x 50E-6; /* 3.27675 */ CNT1 = 0.5 / 50E-6; /* 10000 */ CNT2 = 0.90 x FS / 50E-6; /* 58981.5 */ /* Thus the null input 0.5V and the 90% of FS input is 2.949075V. */ Set the trim-offset-register to zero; Set Right-Shift register to zero (typically zero. See Right-Shifting section); gain_result = 0h; Clamp = FFF8h/2^(Right_Shift_Register); For n = 15 down to 0 begin gain_result = gain_result + 2^n; Force the 90% FS input (2.949075V); Meas2 = read the digital result from the part; If Meas2 >= Clamp then gain_result = gain_result - 2^n; Else Force the null input (0.5V); Meas1 = read the digital result from the part; if (Meas2 - Meas1) > (CNT2 - CNT1) then gain_result = gain_result - 2^n; end; Set the gain register to gain_result; The gain register is now set and the resolution of the conversion will best match the expected LSB. The next step is to calibrate the offset of the DS1859. With the correct gain value written to the gain register, again force the null input to the pin. Read the digital result from the part (Meas1). The offset value is equal to the negative value of Meas1. Meas1 Offset _ Re gister = 4000h - XOR [4000h] 2 The calculated offset is now written to the DS1859 and the gain and offset scaling is now complete.
DS1859
Right-Shifting A/D Conversion Result (Scalable Dynamic Ranging)
The right-shifting method is used to regain some of the lost ADC range of a calibrated system. If a system is calibrated such that the maximum expected input results in a digital output value of less than 7FFFh (1/2 FS), then it is a candidate for using the right-shifting method. If the maximum desired digital output is less than 7FFFh, then the calibrated system is using less than 1/2 of the ADC's range. Similarly, if the maximum desired digital output is less than 1FFFh, then the calibrated system is only using 1/8 of the ADC's range. For example, if using a zero for the right-shift during internal calibration and the maximum expected input results in a maximum digital output less than 1FFCh, only 1/8 of the ADC's range is used. If left like this, the three MS bits of the ADC will never be used. In this example, a value of 3 for the rightshifting will maximize the ADC range. No resolution is lost since this is a 12-bit converter that is left justified. The value can be right-shifted four times without losing resolution. Table 9 shows when the right-shifting method can be used.
Table 9. Right Shifting
OUTPUT RANGE USED WITH ZERO RIGHT-SHIFTS 0h .. FFFFh 0h .. 7FFFh 0h .. 3FFFh 0h .. 1FFFh 0h .. 0FFFh NUMBER OF RIGHT-SHIFTS NEEDED 0 1 2 3 4
Memory Protection
Memory access from either device address can be either read/write or read only. Write protection is accomplished by a combination of control bits in EEPROM (APEN and MPEN in configuration register 89h) and a write-protect enable (WPEN) pin. Since the WPEN pin is often not accessible from outside the module, this scheme effectively allows the module to be locked by the manufacturer to prevent accidental writes by the end user. Separate write protection is provided for the Auxiliary and Main Device address through distinct bits APEN and MPEN. APEN and MPEN are bits from configuration register 89h, Table 01. Due to the location, the APEN and MPEN bits can only be written through the
23
____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Main Device address. The control of write privileges through the Auxiliary Device address depends on the value of APEN. Care should be taken with the setting of MPEN, once set to a 1, assuming WPEN is high. Access through the Main Device is thereafter denied unless WPEN is taken to a low level. By this means, inadvertent end-user write access can be denied. Main Device address space 60h to 7Fh is SRAM and is not write protected by APEN, MPEN, or WPEN. For example, the user may reset flags set by the device. Note that in single device mode (ADEN bit = 1), APEN determines the protection level of Table 00, independent of WPEN. The write-protect operation, for both Main and Auxiliary Devices, is summarized in Tables 6 and 7. age window (between POD and the EEPROM recall) regardless of the programmed state of ADEN. Furthermore, as the device powers up, the VCClo alarm flag (bit 4 of 70h in Main Device) defaults to a 1 until the first VCC analog-to-digital conversion occurs and sets or clears the flag accordingly.
2-Wire Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin may only change during SCL-low time periods. Data changes during SCL-high periods will indicate a START or STOP condition depending on the conditions discussed below. See the timing diagrams in Figures 5 and 6 for further details. START Condition: A high-to-low transition of SDA with SCL high is a START condition that must precede any other command. See the timing diagrams in Figures 5 and 6 for further details. STOP Condition: A low-to-high transition of SDA with SCL high is a STOP condition. After a read or write sequence, the stop command places the DS1859 into a low-power mode. See the timing diagrams in Figures 5 and 6 for further details. Acknowledge: All address and data bytes are transmitted through a serial protocol. The DS1859 pulls the SDA line low during the ninth clock pulse to acknowledge that it has received each word. Standby Mode: The DS1859 features a low-power mode that is automatically enabled after power-on, after a STOP command, and after the completion of all internal operations. Device Addressing: The DS1859 must receive an 8-bit device address following a START condition to enable a specific device for a read or write operation. The address is clocked into this part MSB to LSB. The address byte consists of either A2h or the value in Table 01 8Ch for the Main Device or A0h for the Auxiliary Device, then the R/W bit. This byte must match the address programmed into Table 01 8Ch or A0h (for the Auxiliary Device). If a device address match occurs, this part will output a zero for one clock cycle as an acknowledge and the corresponding block of memory is enabled (see the Memory Organization section). If the R/W bit is high, a read operation is initiated. If the R/W is low, a write operation is initiated (see the Memory Organization section). If the address does not match, this part returns to a low-power mode.
Temperature Conversion
The direct-to-digital temperature sensor measures temperature through the use of an on-chip temperature measurement technique with an operating range from -40C to +102C. Temperature conversions are initiated upon power-up, and the most recent conversion is stored in memory locations 60h and 61h of the Main Device, which are updated every tframe. Temperature conversions do not occur during an active read or write to memory. The value of each resistor is determined by the temperature-addressed look-up table. The look-up table assigns a unique value to each resistor for every 2C increment with a 1C hysteresis at a temperature transition over the operating temperature range (see Figure 4).
Power-Up and Low-Voltage Operation
During power-up, the device is inactive until V CC exceeds the digital power-on-reset voltage (POD). At this voltage, the digital circuitry, which includes the 2-wire interface, becomes functional. However, EEPROMbacked registers/settings cannot be internally read (recalled into shadow SRAM) until VCC exceeds the analog power-on-reset voltage (POA), at which time the remainder of the device becomes fully functional. Once VCC exceeds POA, the RDYB bit in byte 6Eh of the Main Device memory is timed to go from a 1 to a 0 and indicates when analog-to-digital conversions begin. If VCC ever dips below POA, the RDYB bit reads as a 1 again. Once a device exceeds POA and the EEPROM is recalled, the values remain active (recalled) until VCC falls below POD. For 2-wire device addresses sourced from EEPROM (ADFIX = 1), the device address defaults to A2h until VCC exceeds POA and the EEPROM values are recalled. The Auxiliary Device (A0h) is always available within this volt24
____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors
Write Operations
After receiving a matching address byte with the R/W bit set low, if there is no write protect, the device goes into the write mode of operation (see the Memory Organization section). The master must transmit an 8bit EEPROM memory address to the device to define the address where the data is to be written. After the byte has been received, the DS1859 transmits a zero for one clock cycle to acknowledge the address has been received. The master must then transmit an 8-bit data word to be written into this address. The DS1859 again transmits a zero for one clock cycle to acknowledge the receipt of the data. At this point, the master must terminate the write operation with a STOP condition. The DS1859 then enters an internally timed write process tw to the EEPROM memory. All inputs are disabled during this byte write cycle. Page Write The DS1859 is capable of an 8-byte page write. A page is any 8-byte block of memory starting with an address evenly divisible by eight and ending with the starting address plus seven. For example, addresses 00h through 07h constitute one page. Other pages would be addresses 08h through 0Fh, 10h through 17h, 18h through 1Fh, etc. A page write is initiated the same way as a byte write, but the master does not send a STOP condition after the first byte. Instead, after the slave acknowledges the data byte has been received, the master can send up to seven more bytes using the same nine-clock sequence. The master must terminate the write cycle with a STOP condition or the data clocked into the DS1859 will not be latched into permanent memory. The address counter rolls on a page during a write. The counter does not count through the entire address space as during a read. For example, if the starting address is 06h and 4 bytes are written, the first byte goes into address 06h. The second goes into address 07h. The third goes into address 00h (not 08h). The fourth goes into address 01h. If more than 9 bytes or more are written before a STOP condition is sent, the first bytes sent are overwritten. Only the last 8 bytes of data are written to the page. Acknowledge Polling: Once the internally timed write has started and the DS1859 inputs are disabled, acknowledge polling can be initiated. The process involves transmitting a START condition followed by the device address. The R/W bit signifies the type of operation that is desired. The read or write sequence will only be allowed to proceed if the internal write cycle has completed and the DS1859 responds with a zero.
DS1859
Read Operations
After receiving a matching address byte with the R/W bit set high, the device goes into the read mode of operation. There are three read operations: current address read, random read, and sequential address read. Current Address Read The DS1859 has an internal address register that maintains the address used during the last read or write
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure 5. 2-Wire Data Transfer Protocol ____________________________________________________________________ 25
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 6. 2-Wire AC Characteristics
operation, incremented by one. This data is maintained as long as VCC is valid. If the most recent address was the last byte in memory, then the register resets to the first address. Once the device address is clocked in and acknowledged by the DS1859 with the R/W bit set to high, the current address data word is clocked out. The master does not respond with a zero, but does generate a STOP condition afterwards. Single Read A random read requires a dummy byte write sequence to load in the data byte address. Once the device and data address bytes are clocked in by the master and acknowledged by the DS1859, the master must generate another START condition. The master now initiates a current address read by sending the device address with the R/W bit set high. The DS1859 acknowledges the device address and serially clocks out the data byte. Sequential Address Read Sequential reads are initiated by either a current address read or a random address read. After the master receives the first data byte, the master responds with an acknowledge. As long as the DS1859 receives this acknowledge after a byte is read, the master can clock out additional data words from the DS1859. After reaching address FFh, it resets to address 00h.
The sequential read operation is terminated when the master initiates a STOP condition. The master does not respond with a zero. The following section provides a detailed description of the 2-wire theory of operation.
2-Wire Serial-Port Operation
The 2-wire serial-port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device that receives data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1859 operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following I/O terminals control the 2-wire serial port: SDA, SCL. Timing diagrams for the 2-wire serial port can be found in Figures 5 and 6. Timing information for the 2-wire serial port is provided in the AC Electrical Characteristics table for 2-wire serial communications. The following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in
26
____________________________________________________________________
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors
the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low while the clock is high defines a START condition. Stop data transfer: A change in the state of the data line from low to high while the clock line is high defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is one clock pulse per bit of data. Figures 5 and 6 detail how data transfer is accomplished on the 2-wire bus. Depending on the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications, a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1859 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse, which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge can be returned. The master device generates all serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1859 can operate in the following three modes: 1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave (device) address and direction bit have been received. 2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1859, while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. 3) Slave Address: Command/control byte is the first byte received following the START condition from the master device. The command/control byte consists of 4-bit control code. They are used by the master device to select which of eight possible devices on the bus is to be accessed. When reading or writing to the DS1859, the deviceselect bits must match one of two valid device addresses, 00h or the address registered in Table 01 location 8Ch. The last bit of the command/control byte (R/W) defines the operation to be performed. When set to a `1' a read operation is selected, and when set to a `0' a write operation is selected. The slave address can be set by the EEPROM. Following the START condition, the DS1859 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the 1010 control code, the appropriate device address bits, and the read/write bit, the slave device outputs an acknowledge signal on the SDA line.
DS1859
____________________________________________________________________
27
Dual, Temperature-Controlled Resistors with Internally Calibrated Monitors DS1859
Chip Information
TRANSISTOR COUNT: 47,191 SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of DS1859

	To Download DS1859 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .